If the product requires wafer level testing, then more hardware is needed. In addition to a manual test rig, I will also have been designing a probe card, which will connect to the ATE head with a ...

A new technical paper titled “Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip” was published by researchers at Inha University and Teradyne. ...

And here we’ve been complaining about Flat Pack No-Lead chips when this guy is prototyping with Ball Grid Array in a Wafer-Level Chip Scale Package (WLCSP). Haven’t heard that acronym before?